The present invention relates generally to the field of semiconductor processing, and more specifically to a method for improving negative channel metal oxide semiconductor (NMOS) device performance for 0.1 micron or smaller complementary metal oxide semiconductor (CMOS) technology on a semiconductor substrate.
Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices on an integrated circuit chip doubles every two years. Today""s fabrication plants are routinely producing devices having 0.1 xcexcm and even 90 nm feature sizes and smaller. Solving the problems associated with new process implementations and equipment technology as well as device requirements have become increasingly challenging.
High integration chips with shrinking device geometries require substrate processing systems to meet the demands for forming ultra thin MOS gates and ultra-shallow doped regions. With the advent of smaller device geometries, ultra-shallow doped regions in semiconductors are needed for various applications.
Traditional approaches to forming ultra-shallow doped regions, such as ion implantation and gaseous diffusion, are inadequate in some applications. These approaches have only a limited ability to control dopant distribution and junction depth, especially as the doped regions become shallower. Ion implantation control over dopant distribution is difficult due to a concentration of ions which build up at the surface of the semiconductor material. Also, ion implantation causes damage to the semiconductor surface, and methods of repair often create difficulties with controlling dopant distribution and junction depth for ultra-shallow doped regions. For example, ions bombarded at relatively high energy levels have a tendency to tunnel through the semiconductor material causing damage such as point defects. These point defects, which can lead to irregular and non-uniform junction depths, may be fixed by annealing the implanted semiconductor material at high temperatures. However, this annealing of the implanted semiconductor material may increase the junction depth further than desired.
In gaseous diffusion, controlling dopant distribution and junction depth is difficult when forming ultra-shallow doped regions. As technology progresses to allow even smaller geometry devices, an alternative approach which provides greater control over the dopant uniformity and junction depth in ultra-shallow doped regions is needed.
Another method of forming ultra-shallow doped regions is the use of a doped dielectric film as a dopant diffusion source. In this alternative approach, a doped dielectric film is deposited onto a substrate and used as a source of dopants to be diffused into the substrate to form ultra-shallow doped regions. A method and apparatus for use of this doped dielectric film is discussed in U.S. Pat. No. 6,099,647, which is hereby incorporated by reference.
Another process that requires improvement as device geometries shrink is the formation of the gate stack, a critical component of the metal oxide semiconductor field effect transistor (MOSFET). The fabrication of the MOS gate stack, which typically comprises a gate oxide, polysilicon, and sometimes a metal silicide, is becoming more challenging as process technology begins to facilitate production of 0.1 micron geometries and smaller. Due to the sensitive nature of the gate stack fabrication, processing has begun to be performed in single substrate processing chambers. The vacuum environment of these chambers greatly reduces the number of particulates that contaminate the surfaces of the wafers, thereby improving the device yield. A vacuum system may include a central robotic transfer chamber coupled with various processing chambers. One example of this type of vacuum system is the Single Wafer Thermal Process Cell (SWTPC), which can be purchased from Applied Materials Inc. of Santa Clara, Calif. The SWTPC is a front-end, single wafer processing system that includes process modules for gate oxidation via an insitu H2O vapor rapid thermal process chamber, a decoupled plasma nitridation (DPN) process chamber, and a polysilicon deposition chamber.
The increasing problems of excessive gate leakage current in ultra thin oxide and dopant impurity penetration have become major obstacles to the continued downscaling of dual gate CMOS technology. Recently, the use of ultra-thin nitride/oxide (N/O) stack gate dielectric and a decoupled nitrogen plasma source (DPN) has been proposed as a viable alternative to using silicon dioxide as a MOS gate material for 0.1 micron device geometries. These materials have good impurity diffusion barrier properties and low gate leakage current densities. Shrinking the dielectric thickness in nitride/oxide stack film or nitrided oxide, however, is difficult. Pre-gate doping can effectively shrink the NMOS equivalent oxide thickness (EOT) without causing an increase in leakage current. EOT is a value used to compare the performance of MOS gate dielectrics having a dielectric constant greater than SiO2, while having the performance of SiO2 MOS gates. EOT indicates the thickness of SiO2 gate oxide required to obtain a gate capacitance equal to the capacitance obtained with a dielectric thicker than SiO2 and featuring a higher dielectric constant k. For example, the EOT for a 10 nm thick dielectric featuring a k=39 would be 1 nm (k of SiO2 is 3.9). However, pre-gate doping is of only limited use due to an increase in leakage current. The increase in leakage current is due mainly to the enhanced polysilicon gate activation rate which is well know by those skilled in the art.
The present invention provides a method for fabricating a metal oxide semiconductor (MOS) gate stack on a semiconductor substrate. In one embodiment, the method includes generating moisture on a surface of the semiconductor substrate, performing a nitridation process on the moistened substrate, and after the nitridation process, performing a polysilicon deposition process on the surface of the semiconductor substrate. The polysilicon is then cleaned. The cleaning can utilize such features as ammonia hydroxide, megasonic agitation, and de-ionized water.
In some embodiments, the moisture is generated using a rapid thermal oxidation process or a rapid thermal oxy-nitridation process.
In another embodiment, a method is provided for creating a gate for a device in a semiconductor substrate. The method includes forming a relatively thin gate dielectric on the substrate, depositing a layer of polysilicon over the thin gate dielectric, doping the polysilicon to a relatively high doping level, and cleaning the polysilicon layer with a cleaning solution including ammonia hydroxide.
In some embodiments, the relatively high doping level is greater than or equal to 5xc3x971015 at/cm3 and the thin gate dielectric is less than or equal to 10 nanometers in thickness.
In another embodiment, a method is provided for fabricating a metal oxide semiconductor (MOS) gate stack on a semiconductor substrate. The method includes generating moisture on a surface of the semiconductor substrate to form an oxide layer less than 10 nanometers thin and performing a nitridation process on the thin oxide layer. After the nitridation process, the method includes performing a polysilicon deposition process on the surface of the semiconductor substrate, doping the polysilicon deposition to a level of 5xc3x971015 at/cm3, and cleaning the doped polysilicon with a light ammonia solution.
In some embodiments, the step of cleaning further includes performing megasonic agitation and/or sweeping the ammonia solution across the surface of the semiconductor substrate.